Problem 5: Do you 'C' what I'C'? (22 points) Consider a cache with the following specifications: • Byte-addressable memory • 2-Way Set-Associativity • Block Size: 8 bytes • Cache Size: 32 bytes LRU replacement policy Given the following sequence of cache accesses, determine whether each access is a hit or a miss and then classify each of the misses as one of compulsory capacity. or conflict. Additionally, break down each address to show the tag and set index in order to help see what is in the cache. Please follow the format of the first row (which is filled out for you). You can optionally use the infinite Cache, Fully Associative Cache and Set Associative Cache columns to help you simulate different hit/miss scenarios. Address Tag (Binary) Set Hit / Index Miss? Type (N/A if Hit) Infinite Cache Fully Set Associative Associative Ox37 0011 0 Miss Compulsory X X х Ox01 Ox5C Ox00 Ox14 Ox30 Ox58 Ox62 OxF9 Ox07 Ox31 Ox66