suppose the following pipeline is designed for the integer and the floating point parts of the dlx processor. ex is integer alu operation. a1, a2 represent floating point add/subtract and are internally pipelined. m1, m2, m3 represent floating point multiply and also is internally pipelined. dlx pipeline design for the following parts, show the number of clock cycles needed to execute the code, forwarding and feedback requirements, and stall detection logic. divf f8, f3, f4 addf f6, f3, f8 mulf f9, f4, f6 g