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Superscalar pipelines require replication of pipeline resources across each parallel pipeline, naively including the replication of cache ports. In practice, however, a two-wide superscalar pipeline may have two data cache ports but only a single instruction cache port. Explain why this is possible, but also discuss why a single instruction cache port can perform worse than two (replicated) instruction cache ports.

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Answer and Explanation:

Multi-ported cache are required to achieve high performance the reason for the modern microprocessors being in demand.

But since, they are expensive their use is avoided. Thus in order to maintain the high performance we make use of the dual ported cache which are the composition of single port Static or SRAMs.

The performance of a single ported cache is the worst. Multi ported cache provides high performance. Thus the no. of ports affects the performance.

As the no. of load and store operations are same, dual port is used for the separation of the operations of load and store when we access the cache.

This results in the reduction of the delay and helps in achieving high performance of about 98% without any reduction in the processor's performance.

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