Answer:
Below is a possible implementation using D-flip-flops.
Explanation:
Creating a counter that only counts even numbers is easy, just add a dummy bit-0 that is always 0. Creating a counter with D-flip-flops is also quite straightforward. The clock should be connected to the clock of the least significant bit, and the !Q output of the D flip flop should be fed back to the D input. Also, !Q should be used as a clock for the next bit.
Now, letting the counter wrap around to zero at 10 is tricky because of switching hazards. I created an NAND gate that compares the outputs to be 101, and the clock to be 0. Only this way you can guarantee that the outputs are stable. Now the resulting signal has to be delayed for one clock pulse. This can be achieved with an additional flip flop. The Q output of that flip flop operates the async resets of the counter flipflops.
